1. Field of the Invention
The present invention relates to a test method for a semiconductor memory device and the semiconductor memory device therefor, and more particularly to a test method for detecting a sense amplifier which has an unbalanced characteristic, and the semiconductor memory device therefor.
2. Description of the Related Art
Among semiconductor memory devices, Dynamic RAM (DRAM) and pseudo-SRAM which automatically refreshes internally, are facing a problem where the failure of a memory cell and sense amplifier, which are not due to a process failure, are generated as memory capacity increases and size decreases.
As memory capacity increases and size decreases in semiconductor memory devices, the capacitance of the memory cell tends to decrease and the capacitance between adjacent bit lines tend to increase. And dispersion among memory cells increases, and the unbalanced characteristic of the sense amplifier becomes conspicuous. The unbalanced characteristic of a sense amplifier means that the characteristic between a P-channel transistor pair becomes uneven, and/or the characteristic between an N-channel transistor pair becomes uneven in a sense amplifier comprised of a pair of CMOS inverters where input and output are cross-connected. The miniaturization of elements increases the probability of defects concentrating to a specific transistor element, so the characteristic dispersion among transistor elements, not due to manufacturing process, occurs.
In the case of a DRAM, 1 and 0 of data are stored depending on whether charge is stored or not in a capacitor of a memory cell. The charge stored in the capacitor is lost by leak current as time elapses. Therefore in a DRAM, a refresh operation is performed periodically in which memory cells are read and the same data is written again. If the capacitance of a memory cell becomes small due to the increase of memory capacity and miniaturization of the device, the stored charge is lost by leak current in a short time, so the cycle of refresh operation must be shorter. However decreasing the cycle of the refresh operation causes an increase of power consumption, which is not desirable.
Therefore a memory cell of which capacitance of the capacitor of the cell is small and leak current is large, is rejected (excluded) as a failure bit in the refresh operation test, since the stored charge is lost in a short time in such a memory cell.
International Publication, WO 2004/079745 A1 states that when a refresh operation test is performed, the operation test is performed with artificially decreasing the capacitance of the capacitor of the cell. In this patent document, one word line is selected, the sense amplifier is activated, and the bit line pair is amplified, then other word lines are selected in a state where the sense amplifier is deactivated, and an intermediate potential is generated in the bit lines.
Japanese Patent Application Laid-Open No. H04-001999 states that in test mode, an intermediate potential is written in memory cells with setting the word line drive level lower than normal operation time, and the margin of the sense amplifier is checked.